1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device which stores stored information according to whether a charge holding circuit is holding charges or not and for which a refresh operation is unnecessary.
2. Description of the Background Art
A dynamic random access memory (DRAM), one of typical semiconductor memory devices, has a memory cell formed of a transistor and a capacitor and the structure of the memory cell in itself is simple. Such a DRAM is most suitable for realizing higher integration and larger capacity of a semiconductor device, and thus has currently been used for various electronic apparatuses.
In a memory cell of the DRAM, charges of the capacitor, corresponding to stored data, would leak due to various factors and are lost gradually. It means that the stored data is lost over time. Thus, in the DRAM, a “refresh operation” is performed with which data is once read and rewritten before it becomes impossible to detect a voltage change appearing on the bit lines corresponding to the stored data at the time of data reading.
As such, the DRAM, for which the refresh operation should be performed constantly and periodically for every memory cell, is inferior in terms of a high-speed operation and low power consumption to a static random access memory (SRAM) that does not require the refresh operation. The DRAM, however, has a simple memory cell structure and enables higher integration as described above. It has a cost per bit considerably lower than those of the other memory devices, and thus is now dominant in the RAMs.
On the other hand, the SRAM, also one of the typical semiconductor memory devices, does not require the refresh operation indispensable for the DRAM, as described above.
A memory cell of the SRAM has a configuration where a flip flop having two inverters cross-coupled to each other is connected to a bit line pair via transistors. The data stored in the flip flop is in a bistable state, and maintains the state as long as a prescribed power supply voltage is supplied. In this point, the SRAM is completely different from the DRAM in which charges accumulated in the capacitor are lost over time.
The SRAM requiring no refresh operation consumes less power, with which an operation of higher speed than that of the DRAM is expected.
A memory cell of the SRAM, however, generally includes six bulk transistors. It has four bulk transistors even in the case where the load element is formed of a thin film transistor (TFT) (hereinafter, the thin film transistor is also referred to as “TFT”). Herein, the term “bulk” is used to express a transistor that is formed within a silicon substrate, in contrast to the TFT formed on a substrate. Hereinafter, a transistor that is formed within the silicon substrate is referred to as the “bulk transistor”, in contrast with a thin film element formed on a substrate, as is the TFT.
As such, a memory cell of the SRAM including six or four bulk transistors is large in size compared to a memory cell of the DRAM having one bulk transistor, with their difference in area being as large as about tenfold.
As a semiconductor memory device that can realize lower power consumption and higher integration than a DRAM, Japanese Patent Laying-Open No. 7-307445 discloses a technique concerning a semiconductor memory device having a memory cell requiring no refresh operation and operating at a low voltage, where a conductive sidewall is configured for use as a gate electrode, and Coulomb barrier is utilized.
As described above, although the currently dominant DRAM is suitable for higher integration and larger capacity because of its simple memory cell structure, it requires the refresh operation, hindering a high-speed operation and low power consumption.
On the other hand, although the SRAM does not require the refresh operation, it requires six or four bulk transistors. Further, for stabilization of an operation of the SRAM, the current driving capability ratio (also referred to as “cell ratio” or “β ratio”) between the driver and access transistors should be maintained at 2 to 3 or more, and the driver transistor should be designed to have a large gate width, which also causes an increase in size of the memory cell of the SRAM. As such, higher integration and larger capacity cannot be expected with a conventional SRAM.
As such, the conventional DRAM and SRAM both have advantages and disadvantages in terms of properties and structures. With further advance of the IT technologies expected in the future, there is a great expectation for a semiconductor memory device that can satisfy higher performance (higher-speed operation and lower power consumption) as well as higher integration and larger capacity.
Moreover, although the semiconductor memory device disclosed in Japanese Patent Laying-Open No. 7-307445 may allow lower power consumption and higher integration than a DRAM, it would be much more beneficial from the standpoints of development cost, manufacturing cost, compatibility and many other aspects if a semiconductor memory device that can solve the above-described problems can be developed based on the currently dominant DRAM and SRAM and by applying the techniques cultivated in the relevant field.